Yaseen Alkhameri
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This article is about the hardware engineer. For his technical blog, see Yaseen Alkhameri (blog).
Overview
Yaseen Alkhameri blends a practical love of hardware with everyday curiosities. By day he designs and verifies RTL — most recently a compact RV32I RISC‑V core in Verilog that was exercised through ModelSim and Verilator and taken through an OpenLane flow to GDS II. By night you’ll often find him cataloging records, sorting Pokémon cards, or tinkering with mechanical keyboards. He currently serves as president of the Mechanical Keyboards Club at UC Davis.
His work sits at the intersection of pragmatic engineering and systems thinking: FPGA prototyping (Intel M9K BRAM inference), RTL verification, and the full-stack hand-off to physical design. He’s also active in hands-on competitions and collaborations; from building browser-agent tools that won at AgentHacks to community projects like AggieShare (HackDavis Hacker's Choice).
His work sits at the intersection of pragmatic engineering and systems thinking: FPGA prototyping (Intel M9K BRAM inference), RTL verification, and the full-stack hand-off to physical design. He’s also active in hands-on competitions and collaborations; from building browser-agent tools that won at AgentHacks to community projects like AggieShare (HackDavis Hacker's Choice).
Working on…
Pipelining a compact RV32I RISC‑V core (Verilog). Docs, simulation, and FPGA notes are on GitHub:
github.com/alkhameri/riscv-core-verilogYaseen Alkhameri
Yaseen Alkhameri
May 25, 2004 (age 21)
Oakland, California, U.S.